analog-chip-design-agents

Signal-chain budgeting, per-block spec allocation, and feasibility for analog/mixed-signal

Verilog-A/AMS, VHDL-AMS and SystemVerilog real-number modeling, OSDI compilation, connect modules

Topology selection, device sizing/biasing, schematic capture, pre-layout ERC and design review

SPICE analyses (DC/AC/transient/noise), PVT corners and Monte-Carlo spec sign-off

Mixed-signal co-simulation, connect rules, RNM regression, and coverage closure

Analog custom layout — floorplan, matched device generation, symmetry/shielded place and route

DRC, LVS, antenna/ERC and density/DFM sign-off against foundry decks

RC and coupling parasitic extraction and back-annotated post-layout netlist generation

Post-PEX corner and Monte-Carlo simulation, spec re-verification, and tape-out gating

Electromigration, IR-drop, ESD, latch-up and aging (HCI/NBTI) analysis and sign-off

Timing/power/noise characterization and Liberty (.lib) / behavioral model generation

RF/mmWave design — S-parameter, harmonic balance, Pnoise/PAC, IP3 and load-pull

Electromagnetic solving for passives/antennas, S-parameter extraction and lumped-model fitting

Mixed-signal top assembly, boundary/connect rules, chip-level AMS sim and power intent

Analog/RF tool detection, JSON output wrappers, MCP config, and memory distillation

Cross-domain pipeline orchestrator — design_state.json fix_request loop with iteration cap and checkpoints