analog-design-layout

analog-chip-design-agents

Claude Code marketplace plugin — full analog / mixed-signal + RF chip design pipeline. 16 plugins · 14 design domains + infrastructure + meta pipeline orchestrator · open-source and proprietary EDA tool coverage.

🚧 Status: Phase 1 (core analog spine) implemented. The marketplace registry, per-plugin manifests, CI, and the shared design_state.json schema are in place. The core spine — analog-design-circuit, analog-design-simulation, analog-design-infrastructure, and analog-design-meta — is now fully implemented (detailed stage rules, memory wiring, fix_request loop, infrastructure tooling). The remaining 12 domains ship skeleton SKILL/orchestrators (stage sequence, tool lists, QoR metrics) and are filled in across phases 2–6. See PLAN.md for the roadmap and phase order; the Phase column below marks each domain's target phase (1 = implemented).

This marketplace mirrors the architecture of digital-chip-design-agents, re-targeted to the analog/mixed-signal + RF flow.

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Available Plugins

Plugin Name	Domain	Invoke When You Want To...	Phase
analog-design-architecture	Analog Architecture	Budget noise/linearity/power across a signal chain, allocate block specs	2
analog-design-modeling	Behavioral / AMS Modeling	Write/compile Verilog-A/AMS · VHDL-AMS · SystemVerilog RNM; build connect modules	2
analog-design-circuit	Circuit (Schematic) Design	Pick a topology, size/bias devices, capture schematic, run pre-layout ERC	1
analog-design-simulation	Circuit Simulation	Run DC/AC/transient/noise, corners, Monte-Carlo; sign off electrical specs	1
analog-design-ams-verification	AMS Verification	Build AMS testbench, set connect rules, run analog↔digital co-sim, close coverage	2
analog-design-layout	Custom Layout	Floorplan, generate matched devices, place/route with symmetry/shielding	3
analog-design-physical-verification	Physical Verification	Run DRC, LVS, antenna/ERC, density/DFM and sign off	3
analog-design-extraction	Parasitic Extraction	RC + coupling extraction, build back-annotated post-layout netlist	3
analog-design-post-layout	Post-Layout Sign-off	Post-PEX corner + MC sim, re-verify specs, gate tape-out	3
analog-design-reliability	Reliability	EM / IR-drop / ESD / latch-up / aging analysis and sign-off	4
analog-design-characterization	Characterization	Generate Liberty/.lib + behavioral models, characterize timing/power/noise	4
analog-design-rf	RF / mmWave Design	S-param, harmonic balance, Pnoise/PAC, IP3, load-pull for LNA/mixer/VCO/PA	5
analog-design-em	EM Modeling	Solve EM for passives/antennas, extract/fit S-parameter models	5
analog-design-ams-integration	Mixed-Signal Integration	Qualify analog IP, assemble AMS top, chip-level AMS sim	6
analog-design-infrastructure	Infrastructure & Memory	Detect analog/RF tools, deploy wrappers, configure MCP, distil memory	1
analog-design-meta	Pipeline Orchestration	Drive closed-loop spec↔circuit↔layout feedback with iteration cap	1

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Install (preview)

Domains are skeletons until their phase lands; installing now gives you the structure and planned scope, not yet the full flow logic.

/plugin marketplace add github:chuanseng-ng/analog-chip-design-agents
/plugin install analog-design-circuit@analog-chip-design-agents
/plugin install analog-design-simulation@analog-chip-design-agents

A one-step install.sh / install.ps1 and multi-IDE export (Copilot/Gemini/ OpenCode/Codex), matching the reference repo, arrive in Phase 6.

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How It Works

Each plugin installs two things, exactly as in the reference repo:

1. A Skill (plugins/<domain>/skills/<skill>/SKILL.md) — domain knowledge Claude reads before executing: stage-by-stage rules, QoR metrics, supported open-source and proprietary tools, and output requirements.

2. An Orchestrator Agent (plugins/<domain>/agents/<domain>-orchestrator.md) — a subagent that sequences stages, enforces pass/fail criteria, applies loop-back rules when a stage fails, and escalates when human input is needed.

The 14 design domains map to the end-to-end analog/mixed-signal + RF pipeline diagrammed in PLAN.md §3. Cross-domain feedback (e.g. a failed Monte-Carlo run looping back to circuit design) is driven by the meta pipeline orchestrator through a shared design_state.json (schema).

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Repo Structure