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From skidl-skills
Interprets SKiDL ERC output, classifies errors vs. warnings, and provides fix patterns for pin conflicts, floating pins, decoupling, and NC usage. Run after circuit changes or during design review.
How this skill is triggered — by the user, by Claude, or both
Slash command
/skidl-skills:erc-rulesThe summary Claude sees in its skill listing — used to decide when to auto-load this skill
- Before exporting any netlist
Drive strength order (PWR > OUT > BIDIR > TRI > OC > IN > NC)
Must-fix errors — treat as blockers:
NC)Warnings — investigate, suppress only with justification:
erc_assert()erc_assert()Mandatory decoupling:
Every IC VCC pin → 100 nF minimum, named C_DECOUP_*
Intentional NC:
U1['NC1', 'NC2'] += NC
Warning suppression:
erc_assert("expected open-drain", net)
ERC run pattern:
if __name__ == "__main__":
# ... circuit ...
ERC()
Produce this summary line after every ERC run:
"X errors, Y warnings, Z notes. Circuit is [PASS/FAIL]."
npx claudepluginhub nickkraakman/skidl-skills --plugin skidl-skillsPerforms a three-angle review of SKiDL circuits: electrical rules check, architecture sanity against requirements, and code quality. Validates footprints and outputs a severity-sorted report.
Checks KiCad PCB designs for EMC pre-compliance risks (ground planes, decoupling, I/O filtering, etc.) and generates severity-ranked reports with test plans. Supports FCC/CISPR.
Generates KiCad schematics and PCBs from natural language prompts with DRC/ERC checks and AI verification loop. Outputs project files, BOM, and report. Ideal for prototyping boards like iCE40 breakouts.