From atopile-dev
How the Faebryk component library is structured, how `_F.py` is generated, and the conventions/invariants for adding new library modules. Use when adding or modifying library components, traits, or module definitions.
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/atopile-dev:libraryThe summary Claude sees in its skill listing — used to decide when to auto-load this skill
The `library` module (located in `src/faebryk/library/`) contains the collection of reusable components, traits, and interfaces that form the "standard library" of the hardware design language.
The library module (located in src/faebryk/library/) contains the collection of reusable components, traits, and interfaces that form the "standard library" of the hardware design language.
import faebryk.core.faebrykpy as fbrk
import faebryk.core.graph as graph
import faebryk.library._F as F
g = graph.GraphView.create()
tg = fbrk.TypeGraph.create(g=g)
resistor = F.Resistor.bind_typegraph(tg=tg).create_instance(g=g)
src/faebryk/library/_F.py
import faebryk.library._F as F pattern.tools/library/gen_F.py
src/faebryk/library/*.py, detects whether the file contains a same-named class, and writes _F.py.F.<Name> references to avoid import-order cycles.src/faebryk/library/ contains specific component definitions (e.g. Resistor.py, Capacitor.py, LED.py).can_bridge.py, is_power.py).faebryk.library._F (aliased as F).ato built-ins to these classes.can_bridge) and Components for physical things (what it is like Resistor)._F.py is a generated “barrel” module; importing it is intentionally convenient but can be heavyweight.MyComponent.py in src/faebryk/library/. Inherit from Node (or a more specific base)._F.py: run python tools/library/gen_F.py and commit the updated src/faebryk/library/_F.py.test/library/ (including test/library/nodes/).ato dev test --llm test/library/test_instance_library_modules.py -qis_atomic_part trait.F.Parameters to define physical properties like resistance, capacitance, etc.npx claudepluginhub mawildoer/atopile-agent-skill --plugin atopile-devEnforces library-first component lookup, correct Auto Layout structure, and semantic node naming when building UI elements in Figma.
Installs, lists, queries verified hardware IP blocks (FIFO, UART, SPI, AXI) with RTL, testbenches, formal properties into projects via 'add a FIFO' or /gf-ip add uart.
Routes 17 KiCad MCP tools for schematic creation, PCB layout, autorouting, DRC, and Gerber export. Enforces serialized PCB ops and library-first lookup.