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From gateflow
Installs, lists, queries verified hardware IP blocks (FIFO, UART, SPI, AXI) with RTL, testbenches, formal properties into projects via 'add a FIFO' or /gf-ip add uart.
How this skill is triggered — by the user, by Claude, or both
Slash command
/gateflow:gf-ipThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
- `add <block>` — Copy IP block into current project
add <block> — Copy IP block into current projectlist — Show all available IP blocksinfo <block> — Show block details, ports, parameters| Block | Description | Verified |
|---|---|---|
| fifo_sync | Synchronous FIFO (parameterized width/depth) | lint + sim + formal |
| fifo_async | Async FIFO with Gray code pointers (CDC) | lint + sim + formal |
| cdc_2ff | 2-flip-flop synchronizer | lint + sim + formal |
| cdc_handshake | Multi-bit handshake synchronizer | lint + sim + formal |
| uart | UART TX+RX with configurable baud | lint + sim + formal |
| spi_master | SPI master (all 4 CPOL/CPHA modes) | lint + sim + formal |
| axi4lite_slave | AXI4-Lite register slave | lint + sim + formal |
| debouncer | Button debouncer with edge detection | lint + sim + formal |
Each block lives in ${CLAUDE_PLUGIN_ROOT}/ip/<name>/:
<name>/
rtl/<name>.sv # RTL source
tb/tb_<name>.sv # Self-checking testbench
formal/<name>_props.sv # SVA properties
formal/<name>.sby # SymbiYosys config
block.yaml # Metadata
README.md # Usage guide
When user says "add a FIFO" or runs /gf-ip add fifo_sync:
rtl/ (or user-specified directory)tb/formal/.gateflow/project.yaml — add to ip_blocksname: fifo_sync
version: 1.0.0
description: Synchronous FIFO with parameterized width and depth
parameters:
WIDTH: { type: int, default: 8, description: "Data width in bits" }
DEPTH: { type: int, default: 16, description: "FIFO depth (entries)" }
ports:
- { name: clk, dir: input, width: 1 }
- { name: rst_n, dir: input, width: 1 }
- { name: wr_en, dir: input, width: 1 }
- { name: wr_data, dir: input, width: WIDTH }
- { name: rd_en, dir: input, width: 1 }
- { name: rd_data, dir: output, width: WIDTH }
- { name: full, dir: output, width: 1 }
- { name: empty, dir: output, width: 1 }
formal_proofs:
- p_no_overflow: "FIFO never accepts writes when full"
- p_no_underflow: "FIFO never allows reads when empty"
dependencies: []
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowScans FPGA/hardware codebases for missing module implementations, stub modules, standard IP patterns (FIFO, CDC, UART, SPI, AXI), interface gaps, and vendor primitives. Dispatches agents to fill gaps.
Generates convention-compliant SystemVerilog wrapper modules for third-party IP (memory, PLL, PHY, DSP) from IP-XACT descriptors or datasheets.
Guides full Xilinx/AMD FPGA/MPSoC workflows: Vivado hardware design/Block Design/IP/XDC/bitstream, Vitis HLS C/C++ IP synthesis, Vitis embedded software, PetaLinux Linux builds. Activates on vivado/fpga/zynq mentions.