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From gateflow
Performs place-and-route using nextpnr for Lattice iCE40, ECP5, and Gowin FPGAs. Generates bitstreams from Yosys synth.json and constraints. Reports timing and utilization.
How this skill is triggered — by the user, by Claude, or both
Slash command
/gateflow:gf-pnrThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
| FPGA Family | Tool | Command |
| FPGA Family | Tool | Command |
|---|---|---|
| Lattice iCE40 | nextpnr-ice40 | nextpnr-ice40 --up5k --package sg48 --json synth.json --pcf constraints.pcf --asc output.asc |
| Lattice ECP5 | nextpnr-ecp5 | nextpnr-ecp5 --85k --package CABGA381 --json synth.json --lpf constraints.lpf --textcfg output.config |
| Gowin | nextpnr-gowin | nextpnr-gowin --device GW1NR-LV9QN88PC6/I5 --json synth.json --cst constraints.cst |
NOT Supported: Xilinx (use Vivado), Intel (use Quartus). For these, GateFlow generates TCL scripts instead.
which nextpnr-ice40 || which nextpnr-ecp5 || which nextpnr-gowin
If not found:
---GATEFLOW-RESULT---
STATUS: ERROR
DETAILS: nextpnr not installed. Install for place & route.
macOS: brew install nextpnr
Linux: see https://github.com/YosysHQ/nextpnr
---END-GATEFLOW-RESULT---
After P&R:
icepack output.asc output.binecppack output.config output.bit---GATEFLOW-RESULT---
STATUS: PASS | FAIL | ERROR
TIMING:
Fmax: 125.3 MHz
Slack: +2.1 ns
UTILIZATION:
LUTs: 142 / 5280 (2.7%)
FFs: 87 / 5280 (1.6%)
FILES: [output files]
DETAILS: [summary or timing violations]
---END-GATEFLOW-RESULT---
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowSynthesizes SystemVerilog/Verilog designs with Yosys for FPGA targets like iCE40/ECP5/Gowin/Xilinx. Reports LUT/FF/BRAM/DSP utilization, timing, and warns on unsupported SV constructs.
Guides full Xilinx/AMD FPGA/MPSoC workflows: Vivado hardware design/Block Design/IP/XDC/bitstream, Vitis HLS C/C++ IP synthesis, Vitis embedded software, PetaLinux Linux builds. Activates on vivado/fpga/zynq mentions.
Drives an open-source EDA flow from RTL to GDS with signoff checks (DRC, LVS, RCX) using OpenROAD, Yosys, KLayout, and OpenRCX for PPA iteration and flow diagnosis.