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From gateflow
Synthesizes SystemVerilog/Verilog designs with Yosys for FPGA targets like iCE40/ECP5/Gowin/Xilinx. Reports LUT/FF/BRAM/DSP utilization, timing, and warns on unsupported SV constructs.
How this skill is triggered — by the user, by Claude, or both
Slash command
/gateflow:gf-synthThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
```bash
which yosys
If not found:
---GATEFLOW-RESULT---
STATUS: ERROR
DETAILS: Yosys not installed. Install to enable synthesis.
macOS: brew install yosys
Linux: sudo apt install yosys
---END-GATEFLOW-RESULT---
Before synthesis, scan for unsupported constructs:
grep -rn "^\s*interface\s\|^\s*modport\s\|^\s*class\s\|^\s*bind\s" <files>
If found, warn user. Do NOT proceed — it will produce confusing errors.
.gateflow/project.yaml) for target---GATEFLOW-RESULT---
STATUS: PASS | FAIL | ERROR
RESOURCES:
LUTs: N
FFs: N
BRAM: N
DSP: N
TARGET: ice40 | ecp5 | gowin | xilinx | generic
FILES: [synth output files]
DETAILS: [summary or error explanation]
---END-GATEFLOW-RESULT---
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowRuns Yosys synthesis for ASIC area/timing estimation, checks synthesizability, and generates SDC constraints. Detects latches and unmapped cells.
Provides behavioral guidelines to reduce common LLM coding mistakes, focusing on simplicity, surgical changes, assumption surfacing, and verifiable success criteria.