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From gateflow
Generates FPGA constraint files (.xdc/.pcf/.lpf/.cst) with pin assignments, I/O standards, drive strength for boards like Arty A7, iCEBreaker using curated data or web search.
How this skill is triggered — by the user, by Claude, or both
Slash command
/gateflow:gf-pinmapThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
1. **Identify board** — Check `.gateflow/project.yaml` target.board or ask user
.gateflow/project.yaml target.board or ask userls ${CLAUDE_PLUGIN_ROOT}/boards/<board>/board.yaml 2>/dev/null
boards/<board>/board.yaml for pin databoards/<board>/constraints.* for templateOnly when board is NOT in curated database:
"<board name>" constraint file site:github.com"<board name>" pinout .xdc OR .pcf OR .lpfFound constraint data for <board> via web search.
Source: <url>
WARNING: This pin data has NOT been verified against the official
board documentation. Incorrect pin assignments can damage hardware.
Please review before applying:
[show pin assignments]
Apply these constraints? [Y/n]
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowGuides full Xilinx/AMD FPGA/MPSoC workflows: Vivado hardware design/Block Design/IP/XDC/bitstream, Vitis HLS C/C++ IP synthesis, Vitis embedded software, PetaLinux Linux builds. Activates on vivado/fpga/zynq mentions.
Performs place-and-route using nextpnr for Lattice iCE40, ECP5, and Gowin FPGAs. Generates bitstreams from Yosys synth.json and constraints. Reports timing and utilization.
Automates KiCad to EasyEDA to JLCPCB PCB workflow: project setup, LCSC part sourcing, pin-map fetching, fully-wired .kicad_pcb generation via pcbnew, and EasyEDA handoff for routing and ordering.