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From gateflow
Generates FuseSoC .core files from project scans and drives synthesis/simulation via Edalize backends including Vivado, Quartus, Verilator, Yosys. For FPGA/ASIC hardware builds.
How this skill is triggered — by the user, by Claude, or both
Slash command
/gateflow:gf-fusesocThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
Generate FuseSoC .core files and drive builds through Edalize backends.
Generate FuseSoC .core files and drive builds through Edalize backends.
CAPI=2:
name: ::my_project:1.0.0
filesets:
rtl:
files: [rtl/top.sv, rtl/fifo.sv]
file_type: systemVerilogSource
tb:
files: [tb/tb_top.sv]
file_type: systemVerilogSource
constraints:
files:
- constraints/arty_a7.xdc: {file_type: xdc}
targets:
sim:
filesets: [rtl, tb]
toplevel: tb_top
default_tool: verilator
synth:
filesets: [rtl, constraints]
toplevel: top
default_tool: vivado
tools:
vivado:
part: xc7a35ticsg324-1L
| Backend | Tool | Use Case |
|---|---|---|
| verilator | Verilator | Simulation + lint |
| icarus | Icarus Verilog | Simulation |
| vivado | Xilinx Vivado | Synth + P&R |
| quartus | Intel Quartus | Synth + P&R |
| yosys | Yosys | Open-source synth |
Scans project, reads .gateflow/project.yaml, generates .core file.
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowSynthesizes SystemVerilog/Verilog designs with Yosys for FPGA targets like iCE40/ECP5/Gowin/Xilinx. Reports LUT/FF/BRAM/DSP utilization, timing, and warns on unsupported SV constructs.
Guides full Xilinx/AMD FPGA/MPSoC workflows: Vivado hardware design/Block Design/IP/XDC/bitstream, Vitis HLS C/C++ IP synthesis, Vitis embedded software, PetaLinux Linux builds. Activates on vivado/fpga/zynq mentions.
Initializes a new RTL/FPGA/ASIC project with standard directory structure, coding convention rules, and template files for a 6-phase design pipeline.