Orchestrate an automated SoC frontend design pipeline from specification to timing closure using specialized agents for documentation, RTL generation, verification, synthesis, and top-level integration.
SoC CRG (Clock/Reset Generation) 工程师。从 Excel 配置(top_info/clk_gen/rst_gen sheet)生成 CRG 子模块的全部 RTL + SDC,包含 clk_gen.v、rst_gen.v、crg_top.v、寄存器接口。**必须使用 `crg_gen` MCP 工具生成,禁止手写时钟分频/复位同步逻辑**。支持前置 design-flow: 可用 `crg-req-to-design` skill 从需求表生成时钟/复位设计表,再用 `cr-tree-diag-gen` skill 生成拓扑图。该 agent 是 rtl-designer 的特化变体——专门为 CRG 这种 config-driven 的基础设施 IP 设计。当 SoC 需要 CRG 子模块时激活,通常是子模块列表里的第一个。
SoC 设计文档工程师。根据用户需求/objective 编写设计规格书 (design_spec.md)、接口定义 (interface_spec.md)、寄存器映射 (regmap.md)、验证计划 (verification_plan.md)。当主 Agent 接到"设计 X 模块"的需求、需要先把规格落到文档时激活。这是 SoC 流程的第 1 阶段,产物供下游 rtl-designer / verification-engineer 读取。
SoC 顶层集成工程师。在 silicon-crew 项目(用 `soc_init` 初始化过)的 `chip/` 目录下创建顶层模块,把多个已完成 rtl 阶段的子模块集成到顶层。**专属 skill 为 `soc-integrate`,提供端口提取、实例化生成、wrapper 生成、顶层集成、端口变更追踪、filelist 刷新等全套 MCP 工具**。必须使用 `soc_add_chip` 创建顶层目录结构、`soc_integrate` 生成顶层 v、`soc_flist` 更新 filelist.f。**filelist.mk 依赖通过 `include $(PROJECT_ROOT)/.../filelist.mk` 方式声明,严格遵循 skill 模板的 include guard + 自动去重模式**。该 agent 等价于"顶层模块的 rtl 阶段实现",与子模块的 verify/syn 可并行进行。
SoC RTL 设计工程师。根据 docs/design_spec.md + docs/interface_spec.md 编写可综合的 Verilog-2005 RTL,输出 rtl/<module>.v + rtl/rtl.f + constraints/base.sdc。verilator -Wall lint-clean,无 latch 推断。当 doc 阶段完成、需要把规格转 RTL 时激活,是 SoC 流程的第 2 阶段。
SoC 综合工程师。探测目录布局(布局A: Makefile + de/syn/; 布局B: 直接 yosys)。布局A走 `make syn RTL_TOP=<m>`,产物落 `de/syn/`; 布局B用 yosys 综合,产物落 `syn/output/` 和 `syn/reports/`。写时序/面积报告, WNS 必须 >= 0 才算 MET。当验证阶段 PASS、需要综合检查时激活,是 SoC 流程的第 4 阶段。
Clock/Reset Tree Diagram Generator. Convert Excel timing tables into Draw.io (.drawio) and Excalidraw (.excalidraw) diagrams with hierarchical layout, MUX support, root-source edge coloring, and frequency annotations.
Convert CRG requirement table (subsystem, IP, clock/reset signals, notes) into clock tree design table and reset tree design table, with PLL count recommendation and architecture report.
从 Excel 寄存器描述生成 YAML 和 Verilog regfile。
SoC 项目脚手架与仿真基础 skill。提供项目初始化、模块创建、filelist 生成、lint 检查、编译仿真等核心能力。端口提取、顶层集成、CRG/寄存器生成等功能已拆分为独立 skill(soc-integrate、yml2reg、crg-req-to-design、cr-tree-diag-gen 等)。
SoC 顶层集成与端口管理工具,支持 Verilog 端口提取、智能连接、顶层自动生成、端口变更追踪。
Admin access level
Server config contains admin-level keywords
Uses power tools
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Uses Bash, Write, or Edit tools
Uses Bash, Write, or Edit tools
硅农 (Silicon Peasant) 的 Claude Code 智能体插件集合 · agent-driven 芯片设计流水线
silicon-agents 是 @siliconpeasant 的 Claude Code marketplace,装载所有以「智能体协作」方式驱动 SoC / IC 前端工程的插件。一个仓库,统一入口,持续扩展。
Marketplace: siliconpeasant
└── silicon-crew@siliconpeasant ← SoC 前端智能体集合 (4 阶段 + 2 个 rtl 特化)
| Plugin | 版本 | 说明 |
|---|---|---|
silicon-crew | v1.0.0 | 硅农工组 — SoC 前端智能体流水线(doc → rtl → verify → syn),含 CRG / 集成两个 rtl 特化 agent |
路线图(预留位):
silicon-bench(验证 benchmark)、silicon-tape(流片打包专项)、silicon-pdk(PDK 助手)…
在 ~/.claude/settings.json 或项目 .claude/settings.json 加:
{
"extraKnownMarketplaces": {
"siliconpeasant": {
"source": {
"source": "directory",
"path": "/path/to/silicon-agents"
}
}
},
"enabledPlugins": {
"silicon-crew@siliconpeasant": true
}
}
claude plugin marketplace add github:siliconpeasant/silicon-agents
claude plugin install silicon-crew@siliconpeasant
SoC 前端设计 multi-agent 流水线。主 Agent 编排,4 个核心 subagent + 2 个 rtl 阶段特化:
| Subagent | 角色 | 触发 | 产物 |
|---|---|---|---|
soc-doc-engineer | 文档工程师 | 用户提出新模块需求 | docs/*.md |
soc-rtl-designer | RTL 设计(标准) | doc 阶段完成 | rtl/*.v + rtl/rtl.f + constraints/base.sdc |
soc-verification-engineer | 验证 | RTL 阶段完成 | tb/*.v + sim/results/*.log |
soc-synthesis-engineer | 综合 | 仿真 PASS | syn/output/netlist.v + reports + synthesis_report.md |
soc-crg-engineer | RTL 特化:CRG | 子模块是 CRG,Excel 配置驱动 | rtl/*.v(必用 crg_gen MCP)+ rtl.f + base.sdc |
soc-integrator | RTL 特化:顶层集成 | 多子模块 rtl=done,要拼顶层 | 在 silicon-crew 项目 chip/<top>/ 下创建顶层(用 MCP soc_add_chip + soc_integrate + soc_flist),filelist.mk 用 include $(PROJECT_ROOT)/<sub>/de/rtl/filelist.mk 声明依赖,子模块不复制 |
用户需求 ("设计一个 mux2_1, 8-bit")
↓ 主 Agent
├─ spawn soc-doc-engineer → docs/*.md
├─ spawn soc-rtl-designer → rtl/*.v + rtl.f + base.sdc
├─ spawn soc-verification-engineer → tb/*.v + sim/results/*.log
└─ spawn soc-synthesis-engineer → syn/netlist.v + reports
多子模块 SoC 场景:
↓ 主 Agent
├─ N 个子模块各自走 doc → rtl(可并行,CRG 走 soc-crg-engineer)
├─ 子模块 rtl=done → spawn soc-integrator
│ └─ MCP soc_add_chip 在项目 chip/<top>/ 下建模块结构
│ └─ MCP soc_integrate 生成 top.v;MCP soc_flist 刷新 filelist.f
│ └─ Edit filelist.mk 插入 `include $(PROJECT_ROOT)/<sub>/de/rtl/filelist.mk` 引用子模块
│ └─ make lint 走 common.mk 标准流程(子模块 0 拷贝)
│ (与子模块 verify/syn 并行)
└─ 顶层走自己的 verify → syn
soc-build skill + MCP server:Verilog 端口提取、智能集成、wrapper 生成、filelist、lint、Excel/YAML → CRG / Memory Map / Regmapcr-tree-diag-gen skill + MCP server:Excel 时钟/复位表格 → Draw.io (.drawio) + Excalidraw (.excalidraw) 拓扑图(MUX/分频/ICG/复位与门支持,源头边着色,频率标注)所有 subagent 产物落在:
${CLAUDE_PLUGIN_ROOT}/workspace/<task_name>/
<task_name> 由用户指定或主 Agent 推导(小写下划线,如 mux2_1)。
silicon-agents/ ← 仓库 = 市集
├── .claude-plugin/
│ └── marketplace.json ← 市集元数据 (name = siliconpeasant)
├── silicon-crew/ ← 插件 1
│ ├── .claude-plugin/plugin.json ← 插件元数据
│ ├── .claude/CLAUDE.md ← 主 Agent 编排规则
│ ├── agents/ ← 6 个 subagent (4 核心 + 2 rtl 特化)
│ ├── skills/soc-build/ ← Verilog 工具集 skill + MCP server
│ ├── hooks/ ← SessionStart 注入规则
│ ├── rules/ ← 强制规范 (lint/sim/syn 不许绕封装)
│ └── scripts/ ← 每阶段 quality check 脚本
└── README.md ← 你正在看的这个
每个插件一个子目录,内部结构自洽。加新插件只需:
silicon-<name>/ 目录,放好 .claude-plugin/plugin.json + 内容marketplace.json 的 plugins[] 数组追加一项 { "name": "...", "source": "./silicon-<name>" }硅农 (Silicon Peasant) — @siliconpeasant
在硅片上耕作。
TBD
npx claudepluginhub siliconpeasant/silicon-agents --plugin silicon-crewComplete collection of battle-tested Claude Code configs from an Anthropic hackathon winner - agents, skills, hooks, and rules evolved over 10+ months of intensive daily use
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