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Designs sequential logic circuits including latches, flip-flops, registers, counters, and finite state machines. Use when a circuit must remember past inputs or implement state-dependent control.
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/agent-almanac:build-sequential-circuitThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
Design a sequential logic circuit by identifying the required memory and state type, constructing a state diagram and transition table, deriving excitation equations for the chosen flip-flop type, implementing the circuit at the gate level using flip-flops and combinational logic, and verifying correctness through timing diagram analysis and state sequence simulation.
Design a sequential logic circuit by identifying the required memory and state type, constructing a state diagram and transition table, deriving excitation equations for the chosen flip-flop type, implementing the circuit at the gate level using flip-flops and combinational logic, and verifying correctness through timing diagram analysis and state sequence simulation.
Determine what the circuit needs to remember and how many distinct states it requires:
## State Requirements
- **Number of states**: [N]
- **State encoding**: [binary / one-hot / Gray]
- **Flip-flops needed**: [count and type]
- **Machine type**: [Mealy / Moore]
- **Inputs**: [list with descriptions]
- **Outputs**: [list with descriptions]
- **Reset behavior**: [synchronous / asynchronous / none]
Expected: A complete state inventory with encoding chosen, flip-flop type selected, and the machine classified as Mealy or Moore.
On failure: If the state count is unclear from the specification, enumerate states by tracing through all possible input sequences up to the memory depth of the circuit. If the count exceeds practical limits (more than 16 states for manual design), consider decomposing into smaller interacting FSMs.
Formalize the circuit's behavior as a state diagram and equivalent tabular form:
## State Transition Table
| Present State | Input | Next State | Output |
|--------------|-------|------------|--------|
| S0 | 0 | S0 | 0 |
| S0 | 1 | S1 | 0 |
| S1 | 0 | S0 | 0 |
| S1 | 1 | S2 | 0 |
| ... | ... | ... | ... |
- **Unreachable states**: [list, or "none"]
- **Equivalent state pairs**: [list, or "none"]
Expected: A complete state transition table covering every present-state/input combination, with all states reachable from the initial state.
On failure: If the transition table has missing entries, the specification is incomplete. Return to the requirements and resolve the ambiguity. If unreachable states exist, either add transitions to reach them or remove them and reduce the state encoding.
Compute the flip-flop input equations (excitation equations) from the transition table:
## Excitation Equations
- **Flip-flop type**: [D / JK / T]
- **State encoding**: [binary assignment table]
| Flip-Flop | Excitation Equation |
|-----------|------------------------------|
| Q1 | D1 = [minimized expression] |
| Q0 | D0 = [minimized expression] |
## Output Equations
| Output | Equation |
|--------|------------------------------|
| Y | [minimized expression] |
Expected: Minimized excitation equations for each flip-flop and output equations for each primary output, with all don't-cares exploited.
On failure: If the excitation equations seem overly complex, reconsider the state encoding. A different encoding (e.g., switching from binary to one-hot, or reassigning state codes) can dramatically simplify the combinational logic. Try at least two encodings and compare literal counts.
Build the complete circuit from flip-flops and combinational logic gates:
## Circuit Implementation
- **Flip-flops**: [count] x [type], [edge type]-triggered
- **Combinational gates for excitation**: [count and types]
- **Combinational gates for output**: [count and types]
- **Total gate count**: [flip-flops + combinational gates]
- **Reset mechanism**: [asynchronous CLR / synchronous mux / none]
Expected: A complete gate-level netlist with flip-flops, excitation logic, output logic, clock distribution, and reset mechanism, where every signal has exactly one driver.
On failure: If the implementation has feedback outside of the flip-flops, a combinational loop has been introduced. All feedback in a synchronous sequential circuit must pass through a flip-flop. Trace the offending path and reroute it through a register.
Confirm the circuit behaves correctly across multiple clock cycles:
## Timing Verification
| Cycle | Clock | Input | Present State | Next State | Output |
|-------|-------|-------|---------------|------------|--------|
| 0 | rst | - | - | S0 | 0 |
| 1 | rise | 1 | S0 | S1 | 0 |
| 2 | rise | 1 | S1 | S2 | 0 |
| ... | ... | ... | ... | ... | ... |
- **All transitions match state diagram**: [Yes / No]
- **Setup/hold violations**: [None / list]
- **Reset verified**: [Yes / No]
Expected: Every cycle in the timing diagram matches the state transition table, outputs are correct for every cycle, and no timing violations are present.
On failure: If a state transition is wrong, trace the excitation logic for that specific present-state and input combination. If outputs are wrong but transitions are correct, the error is in the output logic. If the circuit enters an unintended state, check for incomplete reset or missing transitions from unused state codes.
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