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From fpga-lsp
Compare two SystemVerilog/Verilog sources with `verible-verilog-diff` for a semantic, SV-aware diff that ignores whitespace and comment-only changes. Use when the user wants to compare two `.sv` files, or two git revisions of the same file, and plain `diff` would be noisy because of formatting or comments.
How this skill is triggered — by the user, by Claude, or both
Slash command
/fpga-lsp:sv-diffThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
Thin wrapper over `verible-verilog-diff`. Use this instead of plain `diff` when whitespace or comment churn would obscure the real changes.
Thin wrapper over verible-verilog-diff. Use this instead of plain diff when whitespace or comment churn would obscure the real changes.
Two distinct files on disk:
verible-verilog-diff <a.sv> <b.sv>
To compare two git revisions of the same path, extract each revision to a temp file first, then diff:
git show <ref-a>:<path> > /tmp/sv-diff-a.sv
git show <ref-b>:<path> > /tmp/sv-diff-b.sv
verible-verilog-diff /tmp/sv-diff-a.sv /tmp/sv-diff-b.sv
The git extraction is the caller's responsibility; this skill is the diff invocation itself.
verible-verilog-diff exits 0 when the two inputs are semantically identical (only whitespace/comment differences, or no differences at all). It exits non-zero and prints a token-level diff when the inputs differ semantically. Treat exit 0 with empty output as "no semantic change".
diffverible-verilog-diff.diff.verible-verilog-format pass: verible-verilog-diff should exit 0.This skill SHALL invoke only verible-verilog-diff. No bespoke comparison logic.
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