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Generates scaffolds for hardware protocols (AXI4-Lite, SPI, UART, I2C, AXI4-Full, AXI-Stream, Wishbone) with testbench templates and integration examples. Useful for requests like 'create I2C master interface' or 'scaffold AXI-Stream source'.
How this skill is triggered — by the user, by Claude, or both
Slash command
/gateflow:gf-protocolsThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
Not production IP cores. Correct, readable scaffolds that engineers customize.
Not production IP cores. Correct, readable scaffolds that engineers customize. Plus the testbenches and integration code — that's where the real time goes.
| Protocol | Priority | Scaffold Includes |
|---|---|---|
| AXI4-Lite | 1 | Slave register interface + master BFM + TB |
| SPI | 2 | Master + slave + loopback TB |
| UART | 3 | TX + RX + loopback TB |
| I2C | 4 | Master + slave model + TB |
| AXI4-Full | 5 | Slave + burst master BFM + TB |
| AXI-Stream | 6 | Source + sink + passthrough + TB |
| Wishbone | 7 | Slave + master + TB |
When user requests a protocol interface:
/gf-ip list)/gf-ip add <block> insteadEach scaffold includes:
Detailed protocol specifications are in references/:
references/axi4-lite.md — AXI4-Lite signal list, timing, rulesreferences/spi.md — SPI modes, timing, signal descriptionsreferences/i2c.md — I2C protocol, addressing, clock stretchingWhen generating scaffolds, ALWAYS read the reference first for correct signal names, widths, and timing requirements.
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowCreates comprehensive RTL implementation plans for hardware designs like DMA controllers, UARTs, and memory subsystems, covering blocks, interfaces, clocks, FSMs, and pipelines.
Enforces SystemC/TLM-2.0 coding standards for BFM and Reference Model development, covering naming conventions, AT/LT patterns, and testbench integration.
Guides full Xilinx/AMD FPGA/MPSoC workflows: Vivado hardware design/Block Design/IP/XDC/bitstream, Vitis HLS C/C++ IP synthesis, Vitis embedded software, PetaLinux Linux builds. Activates on vivado/fpga/zynq mentions.