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Generates Python-based Cocotb testbenches as alternatives to SystemVerilog for hardware verification. Useful for Python-native engineers creating tests for RTL like FIFOs.
How this skill is triggered — by the user, by Claude, or both
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/gateflow:gf-cocotbThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
Generate Cocotb testbenches as an alternative to SystemVerilog TBs.
Generate Cocotb testbenches as an alternative to SystemVerilog TBs.
python3 -c "import cocotb" 2>/dev/null
If not found, return GATEFLOW-RESULT ERROR with: pip install cocotb
import cocotb
from cocotb.clock import Clock
from cocotb.triggers import RisingEdge
@cocotb.test()
async def test_reset(dut):
clock = Clock(dut.clk, 10, units="ns")
cocotb.start_soon(clock.start())
dut.rst_n.value = 0
for _ in range(3):
await RisingEdge(dut.clk)
dut.rst_n.value = 1
await RisingEdge(dut.clk)
assert dut.count.value == 0
| Cocotb | SV Testbench |
|---|---|
| Python (lower barrier) | SystemVerilog |
| Complex stimulus (Python libs) | Protocol + coverage |
| Slower (co-simulation) | Faster (native) |
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflowProvides SystemVerilog testbench best practices including layered architecture, self-checking TBs, transaction classes, and verification patterns. Use for TB structure and methodology.
Executes cocotb-based multi-seed functional regression comparing RTL against reference models, producing a Requirement Traceability Matrix.
Provides behavioral guidelines to reduce common LLM coding mistakes, focusing on simplicity, surgical changes, assumption surfacing, and verifiable success criteria.