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Author, compile, and validate analog behavioral models — Verilog-A, Verilog-AMS, VHDL-AMS, and SystemVerilog real-number models — plus the connect modules that bridge analog and digital domains. This is the analog-HDL core of the marketplace. (Skeleton — full domain rules land in Phase 2.)
How this skill is triggered — by the user, by Claude, or both
Slash command
/analog-design-modeling:behavioral-modelingThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
> **Status: skeleton (Phase 0).** The stage sequence, tool lists, and QoR metrics
Status: skeleton (Phase 0). The stage sequence, tool lists, and QoR metrics below are the planned scope from
PLAN.md§5.2. Detailed per-stage Domain Rules, Common Issues & Fixes, memory wiring, anddesign_state.jsonintegration are implemented in Phase 2.
Author, compile, and validate analog behavioral models — Verilog-A, Verilog-AMS, VHDL-AMS, and SystemVerilog real-number models — plus the connect modules that bridge analog and digital domains. This is the analog-HDL core of the marketplace.
model_planning → va_authoring → model_compilation → connect_rule_setup → model_validation → model_signoff
To be detailed in Phase 2. Each stage above gets numbered, specific
rules, with thresholds sourced from design_state.constraints (see
docs/design_state_schema.md).
Creates, edits, and optimizes skills for Claude Code, including drafting, evaluating with test prompts, iterating on performance, and improving skill descriptions for better triggering accuracy.
npx claudepluginhub chuanseng-ng/analog-chip-design-agents --plugin analog-design-modeling