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From analog-design-ams-integration
Qualify analog IP, assemble the mixed-signal top, define boundary/connect rules, run chip-level AMS simulation, and check power intent through integration sign-off. (Skeleton — full domain rules land in Phase 6.)
How this skill is triggered — by the user, by Claude, or both
Slash command
/analog-design-ams-integration:ams-integrationThis skill is limited to the following tools:
The summary Claude sees in its skill listing — used to decide when to auto-load this skill
> **Status: skeleton (Phase 0).** The stage sequence, tool lists, and QoR metrics
Status: skeleton (Phase 0). The stage sequence, tool lists, and QoR metrics below are the planned scope from
PLAN.md§5.14. Detailed per-stage Domain Rules, Common Issues & Fixes, memory wiring, anddesign_state.jsonintegration are implemented in Phase 6.
Qualify analog IP, assemble the mixed-signal top, define boundary/connect rules, run chip-level AMS simulation, and check power intent through integration sign-off.
ip_qualification → top_assembly → boundary_connect_rules → chip_level_ams_sim → power_intent_check → integration_signoff
To be detailed in Phase 6. Each stage above gets numbered, specific
rules, with thresholds sourced from design_state.constraints (see
docs/design_state_schema.md).
Creates, edits, and optimizes skills for Claude Code, including drafting, evaluating with test prompts, iterating on performance, and improving skill descriptions for better triggering accuracy.
npx claudepluginhub chuanseng-ng/analog-chip-design-agents --plugin analog-design-ams-integration