chipdev-method
Methodology library for chip frontend design — performance model, behavior model, RTL, and behavior↔RTL difftest.
中文版 README
chipdev-method is a Claude Code plugin that codifies a task-oriented methodology
for designing chip frontends. It is knowledge-only and explicit-command-triggered —
it doesn't scaffold code or run automation. Instead, each command returns a
compressed, opinionated set of judgments, invariants, anti-patterns, and minimal
contracts you can apply to your project.
The plugin is organized around what you're trying to do, not what chapter you'd read.
Why this plugin exists
Chip frontend projects routinely produce three artifacts:
- Performance model — cycle-accurate simulator for microarchitecture exploration.
- Behavior model — functional reference model for ISA / dataflow correctness.
- RTL — the synthesizable hardware itself.
These three are usually built by separate teams with separate methodologies, and
the seams between them are where most integration pain lives — interface drift,
state-mismatch in difftest, observability afterthoughts, repeated boilerplate that
should have been generated.
chipdev-method distills a small set of cross-cutting practices that keep these
three artifacts coherent:
- a single-source-of-truth interface DSL that emits all three;
- contract-first design over convention;
- non-blocking advance/idle semantics for performance models;
- behavior models pre-instrumented for RTL difftest;
- commit/transaction-driven sampling with DUT-pushes-ref topology;
- and a Codex-routed audit/diagnose pair for adversarial review and rescue.
Installation
Via Marketplace (recommended)
/plugin marketplace add curryfromuestc/dev-guide
/plugin install chipdev-method@chipdev-method
The first command registers this repository as a Claude Code marketplace.
The second installs the plugin from it.
Prerequisites
- Claude Code v1.x or newer.
- For the
audit and diagnose skills only:
codex-plugin-cc installed
and codex CLI on PATH.
(The other six skills work without Codex.)
Skills
Eight skills, all explicitly invoked via /chipdev-method:<name>.
None of them trigger on implicit keyword detection.
| Skill | Use it when |
|---|
/chipdev-method:choose-artifact | Starting a new chip / module and unsure whether to write performance model, behavior model, or RTL first. |
/chipdev-method:define-contracts | Designing interfaces, state contracts, observability hooks, alignment points, or a single-source-of-truth DSL. |
/chipdev-method:build-perf-model | Implementing a cycle-accurate simulator: scheduler, pipeline primitives, memory abstraction, idle/advance contract. |
/chipdev-method:build-behavior-model | Building a functional reference model that decouples timing but preserves architectural state for difftest. |
/chipdev-method:build-rtl | Writing SystemVerilog — module boundaries, synthesizability, observability instrumentation, lint discipline. |
/chipdev-method:align-and-difftest | Setting up behavior↔RTL difftest: sampling points, drive direction, probes, snapshot debug. |
/chipdev-method:audit | Asking Codex to adversarially review whether your changes follow the methodology. |
/chipdev-method:diagnose | Asking Codex to investigate a build / sim / difftest / perf failure and propose root cause. |
See plugins/chipdev-method/INDEX.md for the
agent-facing routing table.
Methodology in 60 seconds
Six invariants the plugin keeps coming back to:
- Generation over hand-writing. Connection / boilerplate code is generated
from a DSL. Hand-write only the behavioral core of each module.
- Contract over convention. Interfaces are formal contracts (data + protocol
annotation), not naming conventions or doc comments.
- Composition over inheritance. Aggregate subsystems via composition;
reserve inheritance for the generated base class line.
- Configuration over hard-coding. Runtime knobs (sim interval, idle
threshold, dump filters) live in JSON config, not in code.
- Sparse over preallocated. Memory and resources allocate on first touch;
support large address spaces without committing memory upfront.
- Determinism over concurrency. Schedule modules sequentially under a
non-blocking advance(cycles) contract; avoid SC_THREAD-style coroutine
complexity.
These show up across all skills and across all three artifacts.
Provenance and disclaimers
Each skill labels its content with one of:
curryfromuestc
