{"name":"chuanseng-ng-analog-design-modeling-plugins-modeling","owner":{"name":"ClaudePluginHub"},"plugins":[{"name":"chuanseng-ng-analog-design-modeling-plugins-modeling","source":{"source":"github","repo":"chuanseng-ng/analog-chip-design-agents"},"description":"Verilog-A/AMS, VHDL-AMS and SystemVerilog real-number modeling, OSDI compilation, connect modules","version":"0.1.0","strict":true,"keywords":[],"category":"utilities"}]}