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Compiles and runs SystemVerilog testbench simulations using Verilator, auto-detecting DUT files from includes if unspecified, and reports PASS/FAIL based on $display, $error, and $finish.
How this command is triggered — by the user, by Claude, or both
Slash command
/gateflow:gf-sim <testbench> [dut-files...]This command is limited to the following tools:
The summary Claude sees in its command listing — used to decide when to auto-load this command
# GateFlow Simulate Command Compile and run a SystemVerilog simulation using Verilator. > **Note:** The `/gf` orchestrator uses `skills/gf-sim` internally, which provides > structured output (GATEFLOW-RESULT blocks) for automated processing. This command > version is for direct user invocation and provides human-friendly output. ## Instructions 1. **Identify files**: - Testbench file (usually `*_tb.sv`) - DUT files (modules being tested) - If not specified, auto-detect from testbench includes 2. **Compile with Verilator**: 3. **Run simulation**: 4. **Check results**:...
Compile and run a SystemVerilog simulation using Verilator.
Note: The
/gforchestrator usesskills/gf-siminternally, which provides structured output (GATEFLOW-RESULT blocks) for automated processing. This command version is for direct user invocation and provides human-friendly output.
Identify files:
*_tb.sv)Compile with Verilator:
verilator --binary -Wall <dut-files> <testbench>
Run simulation:
./obj_dir/V<top_module>
Check results:
Report outcome:
npx claudepluginhub codejunkie99/gateflow-plugin --plugin gateflow